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US_West | Network Design Engineer_L3

Expedite Technology SolutionsIL

לפני יותר מ-30 ימים

תיאור המשרה

Possible Month CTH | No Fees | Do Not Re-Post | Confidential

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only template

Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include :

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Hiring Status : CC / W / QOpen for CTH (y / n) :

Timeslots for Skype interview (provide Skype ID)

Due to additional onboarding requirements, a meet and greet is required for all new hires.

Candidates must be willing to go to the closest , Client, or offsite location as indicated by project team to meet with a team member prior to starting their assignment.

If the candidate is not local, travel will be required at the expense of the project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors : If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa

OBO Tactical Procurement | Procurement

North America | Guatemala

Email :

Job Description : Logic (RTL) Design Engineer

Location : Santa Clara, CA

No remote, but hybrid option may be negotiated

Roles / Responsibilities :

The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals

Requirements :

Bachelor’s degree in electrical or computer engineering or related field
years of experience in Logic (RTL) Design

Preferred Qualifications :

Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.

Experience with advanced peripheral bus IP’s such as GPIO, UART, SPI, SW, JTAG, and IC.

Strong fundamentals in VLSI design

Strong problem-solving and data analysis skills

Strong skills using scripting languages such as Perl, TCL, Python.

Excellent interpersonal skills and able to work with remote teams

Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Knowledge of low-speed bus protocols (AMBA / OCP) and high-speed serial protocols (PCIe / USB / Ethernet) will used at various stages of the design

Develop HW architecture from specification documents.

Take complete responsibilities include writing RTL code for IP development / RTL integration, checking the code for Lint / CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog / System Verilog / VHDL.

Develop and execute low power design (UPF / CPF).

Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc

Knowledge of JESDC block design and related design / verification experience (includes licensed IP & PHY from rd parties)

Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.

Carry out static checks including Lint / CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.

Take ownership of tasks and drive tasks to closure.

Synopsys / Cadence EDA Tools (Preference : )

Design Compiler (Preference : )

Spyglass Tools (Preference : )

Python (Preference : )

צור התראת עבודה עבור חיפוש זה

Design • IL