US_West | Network Design Engineer_L3

Possible Month CTH | No Fees | Do Not Re-Post | Confidential

Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.

Submit candidates under their legal name and use only template

Candidate’s photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.

In your submission include :

Phone :

Email address :

Location (City and State) :

Relocate :

Availability to start :

Visa type and expiration date :

Hiring Status : CC / W / QOpen for CTH (y / n) :

Timeslots for Skype interview (provide Skype ID)

Due to additional onboarding requirements, a meet and greet is required for all new hires.

Candidates must be willing to go to the closest , Client, or offsite location as indicated by project team to meet with a team member prior to starting their assignment.

If the candidate is not local, travel will be required at the expense of the project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to

Vendors : If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.

Marie Samayoa

OBO Tactical Procurement | Procurement

North America | Guatemala

Email :

Job Description : Sr Logic Design Engineer

Location : Client Specific Location : Austin, TX

No remote, but hybrid option may be negotiated

Good technical leadership skills with ability to guide the CWFs on SoC execution

Should have a good understanding of SoC architecture and should be able to map the Arch spec to implementation level details

Experience in PCIe and Ethernet IP integration

Hands on experience on AMBA based bus protocols

Excellent communication skills is a must

SoC Design engineer with experience working on SOCs based on ARM Architecture

Should be familiar with AMBA based bus protocols like CHI, AXI, AHB, APB etc.,

Hands on experience in integration of PCIe and Ethernet Ips

Good knowledge on design static checks like CDC, RDC, CLP etc.,

Hands on experience on chip IO integration

Desirable to have working knowledge on GIT

• Bachelor’s degree in electrical or computer engineering or related field
• years of experience in Logic (RTL) Design

Preferred Qualifications :

Synopsys / Cadence Tools (Preference : )

Design Compiler (Preference : )

SpyGlass Tools (Preference : )

Python (Preference : )